DxRNG - Discretix RNG Cryptographic Engines
Discretix Cryptographic EnginesDiscretix cryptographic engines are widely deployed in leading system-on-chip solutions. Discretix provides highquality, ready-to-use cryptographic engines, to support variety of applications. Included in Discretix’s family of cryptographic engines are symmetric ciphers, asymmetric ciphers, Hash and random number generators. DxRNG - General DescriptionThe DxRNG provides a full implementation including true and pseudo random number generation. Random numbers are primarily used in cipher key generation for secure data communications, secure data storage and timers in communication protocols. The DxRNG includes two RNG cores. The TRNG core provides True Random Number Generation, with continuous auto correlation self-test of bit stream. The TRNG core eliminates noise generation and checks for random bit stream bias. The PRNG core provides generation of pseudorandom bit stream based on a given seed. The seed can be provided either directly from the TRNG core or by the host processor through a register interface. The two RNG cores (TRNG and PRNG) are easily integrated together to provide a complete RNG solution, or can be used as stand alone modules. The DxRNG engine has two main interfaces: A CPU interface for configuration and random bits collection, and an interface to a source of entropy. Once random bits are read, a new random set of bits is generated. RNG engine
RNG Configuration Options
Key Features
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Key Benefits:
- Digital Right Management schemes (OMA DRM, PlayReady)
- WLAN applications (IEEE 802.11)
- IPSec and SSL/TLS
- WiMax applications (IEEE 802.16)
- Storage – SAN/NAS applications (IEEE P1619)
- E-commerce (EMV v4.1)
Benefits
- Silicon proven – deployed devices and platforms
- Vast experience with multiple tier-1 customers
- Mature technology from the embedded security market leader
- Fast time to market, easily integrated
- Highly optimized implementation ensures minimal gate count and reduced power consumption
- Excellent technical support
Certifications
- FIPS ready
- Common Criteria EAL4+ ready
Deliverables
- Synthesizable Verilog RTL source code
- Synthesis script and constraints
- RTL Test Bench (test vectors and expected results)
- User Manual with hardware integration guidelines and application notes