Discretix Cryptographic Engines
Discretix cryptographic engines are widely deployed in leading
system-on-chip solutions. Discretix provides high-quality,
ready-to-use cryptographic engines, to support variety of
applications. Included in Discretix’s family of cryptographic
engines are symmetric ciphers, asymmetric ciphers, Hash and
random number generators.
DxAES - General Description
The cryptographic engines implement the AES algorithm
for all three key sizes (128-bit, 192-bit and 256-bit). The
AES engine supports multiple modes including: Electronic
Code Book (ECB), Cipher Block Chaining (CBC), Cipher Block
Chaining Message Authentication Code (CBC-MAC) and Counter
(CTR). The engine also supports a dual-tunnel configuration,
where decryption with one key is concatenated by encryption
with another key, avoiding multiple data fetches. DxAES has
three interfaces: configuration (CPU), Data-In and Data-Out.
The CPU interface is a synchronous slave bus which allows
an external processor to access the engine’s configuration
registers. The Data-In and Data-Out interfaces are FIFO-type
interfaces, which are used to stream-in cipher/plain data to
be processed, and stream-out plain/cipher output data. AMBA
AHB interfaces for Data-In and Data-Out are also available.
AES Block Diagram
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Key Applications |
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Digital Right Management schemes (OMA DRM, PlayReady) |
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WLAN applications (IEEE 802.11) |
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IPSec and SSL/TLS |
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WiMax applications (IEEE 802.16) |
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Storage – SAN/NAS applications
(IEEE P1619) |
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| Benefits |
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Silicon proven – deployed in numerous devices and platforms |
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Vast experience with multiple tier-1 customers |
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Mature technology from the embedded security market leader |
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Fast time to market, easily integrated |
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Highly optimized implementation ensures minimal gate count and reduced power consumption |
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Excellent technical support |
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| Certifications |
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FIPS ready |
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Common Criteria EAL4+ ready |
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| Deliverables |
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Synthesizable Verilog RTL source code |
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Synthesis script and constraints |
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RTL Test Bench (test vectors and expected results) |
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User Manual with hardware integration guidelines and application notes |
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AES Configuration Options
The DxAES engine is available in various configurations, supporting a wide range of throughput requirements and desired gate counts.
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Name
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Configuration¹ |
Dual Tunnel |
Keys |
Throughput |
Maximum Clock Frequency |
Gate Count²
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bits/cycle |
Maximum
(in Mbps) |
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DxAES-01
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ECB,
CBC,
CBC-MAC,
CTR |
- |
128 |
3.05
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670 |
220MHz |
16K |
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DxAES-02 |
- |
128 |
10.67 |
2400 |
225MHz |
24K |
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DxAES-03 |
- |
128
192
256 |
3.05
2.56
2.21 |
670
510
440 |
200MHz |
21K |
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DxAES-04 |
- |
128
192
256 |
10.67
9.14
8.00 |
2025
1735
1520 |
190MHz |
31K |
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DxAES-05 |
+ |
128
192
256 |
1.52
1.28
1.11 |
335
255
220 |
200MHz |
27K |
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DxAES-06 |
+ |
128
192
256 |
5.33
4.57
4.00 |
1010
865
760 |
190MHz |
37K |
- Optional support for XCBC mode in all configurations with additional 1.2K Gate
- Technology and synthesis dependent; based on the use of design compiler and low
power 0.09μm TSMC technology; measured at 100MHz
Key Features
- Throughput up to 2400 Mbps
- Supports ECB, CBC, CBC-MAC and CTR modes (according to FIPS SP 800-38A)
- Supports 128, 192 and 256 bits key sizes
- Support for dual-tunneling
- Includes HW Key expansion
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- Internal register file
- Area: 16K - 37K ASIC gates
- Asynchronous 32 or 128-bit data interface
- FIPS PUB 197 compliant
- Optional support for AMBA AHB data interface
- Optional support for XCBC mode
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